A Framework based on Boolean Satisfiability for Soft Error Rate Computation in Early Design Stages

Soft errors, due to cosmic radiations, are the major reliability barrier for VLSI designs. The vulnerability of such systems to soft errors grows exponentially with technology scaling. To meet reliability constraints in a cost-effective way, it is critical to assess soft error reliability parameters in early design stage to optimize reliability in the entire design cycle. Unlike soft error modeling for gate-level netlists, soft error propagation models for high-level behavioral design are not straightforward. In this paper, we present a framework to accurately obtain soft error rate (SER) for high-level (behavioral) descriptions (Verilog or VHDL) in early design stages. We transform the SER computation problem into equivalent Boolean satisfiability problem and use state-of-the-art SATsolvers to obtain SER. We compare our technique to traditional fault simulation techniques. Experiments are carried out on several benchmarks and results are presented.